This invention relates to clock receiver circuits for receiving system clock signals on an integrated circuit chip. The invention encompasses both a differential amplifier circuit used in a clock receiver arrangement and a method for receiving system clock signals.
Integrated circuit systems utilize very sophisticated clock signals for operating and synchronizing the various components of the system. Clock signals are generated by a system clock and distributed to the various chips associated with the system. Each chip which receives the system clock signals utilizes the signals to produce an internal or on-chip clock signal which is then distributed within the chip.
Ideally, the clock signal at any point in the system should provide an identical reference signal. However, due to the complexity and size of integrated circuit systems, various delays appear in the system between clock signals at various points in the system. This difference between the clock signals at various points in the system may be referred to as skew or clock error and directly penalizes the cycle time of the system.
One source of clock skew or error arises in the arrangement for receiving system clock signals on chips included in the system. The system clock signals, which comprise two complementary or differential clock signals, are received on the chip by a clock receiver circuit which converts the differential system clock signals to a single-ended clock signal. The single-ended clock signal from the clock receiver circuit is applied to one input of a phase-lock loop circuit. The output of the phase-lock loop circuit is distributed to the various components on the chip through a clock distribution arrangement or network. The signal from the clock distribution arrangement is fed back and applied as the second input of the phase-lock loop circuit. The phase-lock loop circuit is used in the receiving arrangement to ensure that the distributed on-chip clock signal at the clock distribution arrangement is frequency-aligned and phase-aligned with the system clock signals.
The problem in this system clock receiver arrangement is the difference in the delay between the system clock and the phase-lock loop circuit as compared to the delay introduced in the phase-lock loop feedback path from the on-chip clock distribution arrangement. The receiver circuit introduces a certain delay between the system signals and the signals fed as the first input to the phase-lock loop circuit. In order to reduce skew, there should be an identical delay in the feedback loop of the phase-lock loop circuit. However, it has heretofore proven difficult to accurately produce a delay in the phase-lock loop feedback path which is consistently equal to the delay introduced by the clock receiver circuit. One reason for this is that the differential to single-ended signal conversion required by the clock receiver circuit is not a function required in the feedback path. Various circuit elements may be added to the feedback loop to introduce a delay which is intended to correspond to the delay introduced in the clock receiver circuit. However, these introduced elements behave differently than the elements of the clock receiver circuit under various conditions, and thus the delay introduced by these introduced circuit elements in the feedback loop commonly varies from the delay introduced by the clock receiver circuit.